Author Archives: nosnhojn

About nosnhojn

I've been working in ASIC and FPGA development for more than 13 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. In 2008 I took an interest in agile software development. I've found a massive amount of material out there related to agile development, all of it is interesting and most of it is applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully. I've been fortunate to have the chance to speak about agile hardware development at various conferences like Agile2011, Agile2012, Intel Lean/Agile Conference 2013 and SNUG. I also do lunch-n-learn talks for small groups and enjoy talking to anyone with an agile hardware story to tell! You can find me at neil.johnson@agilesoc.com.

Knowing What Not to Know

My kids play a game where they pick out people and argue about what their superpower is. If we’re all indeed born with a superpower, I’d have to say mine is ignorance. Admittedly – and, yes, unfortunately – this is a superpower … Continue reading

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Posted in Agile | 1 Comment

SVUnit Moved to GitHub

Heads-up that we’ve moved SVUnit from Sourceforge to GitHub. This move was a long time coming, finally got it done a couple weeks ago. From now on, all new development will take place in the SVUnit GitHub repository. We may continue … Continue reading

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My RTL is Done

Kind of. I regularly hear that part of why designers don’t have time for unit testing RTL is because they’re under extreme pressure to deliver RTL to PD. I have very little experience in this direction but I think it’s so … Continue reading

Posted in Agile, design | 5 Comments

5 Steps to Unit Testing Success

Seeing unit testing catch on and flourish with a new team has made the last few months at work pretty fun for me. Getting to this point, though, has been a ton of work. Considering the journey toward unit testing can … Continue reading

Posted in Functional Verification | Leave a comment

Simple Clock and Reset Support in SVUnit

In a post a couple weeks ago called Sorry Design Engineers, I Can Do Better, I told design engineers that I’d do a better job of giving them what they need to unit test their RTL. I felt like I’ve … Continue reading

Posted in Functional Verification | Tagged | Leave a comment

SVUnit Topics, Questions and Opinions

I’m looking for a list of discussion topics for a panel discussion that’ll happen at DAC in June. It’ll be a very informal/interactive session. We’ll take a list of topics and cycle through them in a series of 5-10min discussions. Audience will … Continue reading

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SVUnit for Chip Leads and Managers

Advanced verification methods put chip leads and managers at a real disadvantage, especially when it comes to visibility and predictability. With long testbench development times, early progress in constrained random is essentially based on trust; being random, the inherent uncertainty makes predictable … Continue reading

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Sorry Design Engineers, I Can Do Better

There were a lot of highlights from DVCon when it comes to SVUnit. In fact, it was the most successful three day stretch I’ve had in a very long time. From verification engineers in particular, it was the first time I had … Continue reading

Posted in design | Tagged | 2 Comments

Join the SVUnit User Group

One suggestion that came out of the SVUnit User Group Lunch last week during DVCon was a mailing list so that SVUnit users could keep in touch with questions, etc. Sounded good to me so I’ve set up an SVUnit User … Continue reading

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2 Great Days for SVUnit

The last 2 days at DVCon have been about the best possible for SVUnit. Maybe even better than that. First was the poster sessions on Tuesday just before lunch. Josh Rensch and I had a paper called Do You Verify … Continue reading

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