Author Archives: nosnhojn

About nosnhojn

I have been working in ASIC and FPGA development for more than 12 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. My specialty for most of that time has been RTL functional verification where I have had a chance to work with some very experienced people and learn state of the art techniques. I really enjoy the challenges of being a verification engineer but as of late have come to wonder what lies beyond my verification bubble. That's lead me to agile software development and project management. There is a massive amount of material out there related to agile development. All of it is interesting and most of it should be applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully! You can find me at

SVUnit Adds Support For Aldec Riviera-PRO

Here’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can … Continue reading

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Yes… This is an AgileSoC Shirt

So I’ve been waiting for about 5 years now for someone to turn our AgileSoC logo into a shirt and send it to me without me asking. 5 Years! Ok… not entirely true. I haven’t been waiting for an AgileSoC … Continue reading

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SNUG Unit Testing Finale

SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I … Continue reading

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UVM-UTest File-a-Bug Challenge at SNUG

Time for another UVM challenge… So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll … Continue reading

Posted in Functional Verification | Tagged | 2 Comments

Help Wanted: Need Hecklers for my SNUG Unit Testing Talk

Next week is SNUG in San Jose and I’m looking forward to it. I’ll be presenting How UVM Makes the Case For Unit Testing in the Verification I track from 10:30-12 on Tuesday morning and would love to see some AgileSoC … Continue reading

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Forget About the Verification Gap

I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there … Continue reading

Posted in Functional Verification | 1 Comment

You’re Either With Me Or You’re With: The UVM Register Package

Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was … Continue reading

Posted in Functional Verification | Tagged | 7 Comments

SVUnit Scripting Proposal

I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, … Continue reading

Posted in Functional Verification | Tagged | 4 Comments

Upcoming Changes to SVUnit

After some back-and-forth with SVUnit users over the last several months, I reckon it’s finally time to get rid of the make user interface. Turns out, the incremental construction of the framework that make helped with isn’t all that necessary. … Continue reading

Posted in Functional Verification | Tagged | 1 Comment Has It’s Own EDA Playground

Thanks to a new embeddable version of EDA Playground, you can now test-drive SVUnit right here on! Below, you’ll find the SVUnit example I explained back in December in a post called Demo SVUnit on Code editing is the same, … Continue reading

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