Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was cool and verification was where junior engineers started. Constrained random verification hadn’t hit the mainstream. There wasn’t much functional coverage to speak of. I think Specman and Vera were around but the user-base was relatively small. There was no Systemverilog and there was no UVM. Basically, we were back in the stone age of directed testing. Any knucklehead could do it. Thankfully, I was perfectly qualified. Continue reading
I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, create_svunit.pl + makefiles are out; runSVUnit is in.
Here’s a dump of the runSVUnit usage. Still subject to change so if you see something you don’t like or you don’t see something you would like, now is the time to bring it up :).
Some additional notes… Continue reading
After some back-and-forth with SVUnit users over the last several months, I reckon it’s finally time to get rid of the make user interface. Turns out, the incremental construction of the framework that make helped with isn’t all that necessary. It also seems some hardware developers get a little nervous around makefiles (admittedly, they make me nervous at times). In response, I’ll be putting together a simpler build/run script in place of what’s there now.
If you’re in favour of a new scripting interface and would like to help out by critiquing a first release, please let me know at email@example.com.
I have unit tests for the scripting to rely on for quality so what I end up with should be pretty solid. Still, it’d be nice for me to get a few opinions before I release it.
Thanks to a new embeddable version of EDA Playground, you can now test-drive SVUnit right here on AgileSoC.com!
Below, you’ll find the SVUnit example I explained back in December in a post called Demo SVUnit on EDAPlayground.com. Code editing is the same, running a sim is the same. The only difference (because of our wordpress stylesheet) is that the frame is a little narrower. Other than that, this is our own EDAPlayground right here on AgileSoC.com.
This example is an easy introduction to SVUnit. Start with the instructions in the left pane (you can adjust the pane size to make it easier to read and edit). Then you can bounce over to the design pane. To simulate the example, look for the button in the top right. Click that and you’ll see the run button.
Good luck! Please use the comments to let us know what you think!
Received a very nice endorsement for SVUnit today from a new user doing FGPA development and running Modelsim…
Our company focuses on FPGAs. SVUnit is a GAME CHANGER for FPGAs. FPGAs are different from ASICs, in that bugs can be fixed while the product is in the field. SVUnit is a lot less cumbersome than traditional verification. This allows R&D to push a design into test sooner with similar confidence.
- quick to setup
- does not require expensive licenses
- easy to test individual modules and therefore pin point bugs earlier in development, making the bugs less expensive
(Here’s something cool. I am using the altera starter edition of modelsim under linux. There is a lot of validation people can do without needing a license.)
Nice to hear comments like this. SVUnit is supposed to be clean and user friendly so it’s nice to add another happy user. If you’re ready for a game changing experience, the SVUnit Getting Started page is a good place to start.
PS: Out-of-the-box, SVUnit now supports Modelsim in addition to VCS, Incisive and Questa.
If you’re a hardware developer, here’s a verilog coding exercise you should never, ever attempt.
No one in their right mind would try it; not even dare someone else to try it. The stakes are way too high and you can’t risk your precious time futzing away on some impossible coding exercise. That’s right: impossible. This coding exercise is like doing a 49×49 sudoku on a double black diamond on a 50ft wave at high noon in the middle of a desert that has lots of spiders and rabid skunks… blindfolded. Continue reading
With Cadence recently releasing an eUnit test framework with Specman, I figured now would be a good time to suggest a 2014 new year’s resolution for each of the Big 3:
Make functional verification manageable by releasing a SystemVerilog unit test framework with your simulator.
Don’t worry if that sounds complicated because it isn’t. In a couple months, tops, you could have everything you need to package a first release. All it takes is 4 easy steps.
NOTE (to Mentor/Synopsys): Cadence is winning this race so far. If I had to guess, I’d say that their recent additions to Specman mean they’re considering something similar for SystemVerilog if not well into its development. Continue reading
We can’t leave 2013 without a ‘best of’ summary. Here’s the most read 2013 AgileSoC.com posts for 2013…
Why Agile Will Never Work in Hardware: Of course. This makes complete sense. A post with all the reasons why agile can’t work in hardware was the most popular new entry of 2013.
Time to Blow-up UVM: In this post, I propose an alternative direction to that of UVM; a verification framework with a radical opt-in approach. We’re talking a real platform with (truly) independent pieces as opposed to the hyper-integrated UVM.
Planning to Fail in Hardware Development: This was the first of several posts with analysis of hardware development planning practices based on the 2012 survey I did with Catherine Louis. Lots of interest data here for those who missed it. Worth a look.
You’re Either With Me Or You’re With: The UVM Sequencer: OK… so I tend to pick on UVM a bit. Here’s a post where I talk about some of the unnecessary complexity of UVM sequencer.
How Do Verification Engineers Waste 2 Hours, 52 Minutes, 48 Seconds a Day?: Rounding out the top 5 is analysis of the Mentor Graphics verification survey. (Hint: it has to do with debugging garbage code).
Honorable mention goes to the most read AgileSoC.com reigning champion of all time (by a mile): Emacs, org-mode, Kanban, Pomodoro… Oh my…. That’s Bryan. He’s an Emacs guys. Please… someone needs to post an entry on kanban with VIM already ;).
Thanks for a successful 2013! Hope we’ll see you back in 2014 for more AgileSoC.com!
Yes… I know it’s a good tool. People I respect use it and love it. It’s not that I have any specific complaints about Specman, it’s just that I grew up with Vera and SystemVerilog and with the universal support and attention SystemVerilog gets, I’ve never had the urge to try Specman…
…though it seems tool developers at Cadence are trying to change my mind. Continue reading
Started my day with some encouraging observations that I wanted to share…
First, Victor Lyuboslavsky has posted a couple of youtube videos where he covers some of the basics of unit testing and SVUnit. These are good beginner videos that show how easy it is to get started with SVUnit by kicking the tires on www.edaplayground.com. You can find the videos on youtube. When you’re done with the videos, you can carry on with this online SVUnit tutorial.
Next, an interesting bit of news for fans of unit testing that use Specman, in Victor’s introductory video he mentions Cadence has added unit test capabilities to Specman appropriately named eUnit. You can see more in their Testing the Testbench webinar that was posted last week. I haven’t seen the video yet (having problems logging into the site) so I’ve seen none of the details. Regardless, it’s encouraging to see one of the big 3 pushing unit testing with a new test framework. (I’ll post a follow-up once I’ve seen the webinar).
Lastly… and yes, it may be a little early for this but I’ll throw it out there anyway… on the DVCon2014 program site I see a paper entitled Applying Test-Driven Development Methods To Design Verification Software In UVM-e from Doug Gibson and Michael Kontz of HP. If you’re planning to take in DVCon, be sure to add that talk to your list.
Happy Monday ;).