Tag Archives: UVM

You’re Either With Me Or You’re With: The UVM Register Package

Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was … Continue reading

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Posted in Functional Verification | Tagged | 7 Comments

Why the UVM Boat Anchor Matters

If you saw the UVM boat anchor announcement last week you may have thought a 34 second ascii animation of a sailboat getting caught in the rain is a few hours of my time flushed down the drain and lost forever. Not true. … Continue reading

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Poll: Unit Testing Abstract for DVCon 2014… Yay or Nay?

DVCon call for papers hit my inbox last week. This time around, to possibly save myself the effort, I figured it might be more productive to let other people decide whether or not mine is a topic they’d like to see … Continue reading

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UVM Is Not A Methodology (The TDD Remix)

Forgot about this in last week’s post! Another interesting question from the functional verification seminar I delivered in Mountain View a few weeks ago was: if you could only pick one or the other, would you rather use UVM or … Continue reading

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How UVM-1.1d Makes The Case for Unit Testing

The point of the open-source UVM-UTest project we’ve been working on is to demonstrate how unit tests can be used to lock down the functionality of legacy code. Being able to run the unit tests means that when you’re changing … Continue reading

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Verifying UVM Error Conditions with SVUnit UVM Report Mock

Verifying error conditions and UVM testbench checkers just got easier! The SVUnit UVM report mock lets you automate testing of UVM errors and fatals to increase confidence that the checkers in your testbench are defect free. The SVUnit UVM report mock … Continue reading

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How Do You Feel About The UVM?

I’ve had a lot of reading and commenting on my last post Time to Blow Up UVM. Now I’m looking for an anonymous show of hands to see if I’m on the mark or completely out to lunch regarding UVM. -neil

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Time to Blow Up UVM

Just as it seems the verification community has converged on a methodology – a universal methodology as it were – that finally meets the needs of EDA vendors, IP providers and users, along comes somebody to suggest we should blow … Continue reading

Posted in Functional Verification | Tagged | 38 Comments

UVM Express: So Close Yet…

I think it’s been about 9 months since Mentor Graphics announced UVM Express. While I hope people are seeing value in the idea of UVM Express, I haven’t heard much about it since it was announced which makes me wonder … Continue reading

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UVM Express Step 2: SVUnit with Covergroups and UVM Agents

I can honestly say that as of a couple weeks ago, I’ve gone further with SVUnit than I thought was realistic when I first starting looking at it. Having done more TDD, written more tests and recently finished step 2 … Continue reading

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