Tag Archives: TDD

Stepping Through an RTL Unit Test

Pretty much every testbench I’ve ever built, used or seen has a free-running clock that’s driven within a while or forever loop. Not much can happen without the clock in a synchronous design so defining the clock logic is usually the first and … Continue reading

Posted in Agile | Tagged | 3 Comments

TDD for Design Proof-of-Concept

It’s finally time to see if TDD is a viable technique for writing RTL with verilog. But first, a little backstory… For the Agile2014 conference in Orlando this past summer, Soheil and I built an Agile hardware/software co-development demo using a Xilinx … Continue reading

Posted in Agile | Tagged | 4 Comments

Agile SW/HW Co-development at Agile2014

So 2014 is only a few months old and already it’s been pretty interesting for me. Since January, I’ve had 3 major agile hardware opportunities fall into my lap. Those 3 opportunities have somehow turned into another opportunity that I’m quite excited about. More … Continue reading

Posted in Agile Development | Tagged | 3 Comments

Your Coverage Model is Wrong!

Here’s the scene: you’re a hardware engineer at a conference sitting in on a talk about functional coverage. You’re there because you think functional coverage is important. You think you do a good job of building functional coverage groups but … Continue reading

Posted in Functional Verification | Tagged , | 3 Comments

TDD Applied To Testbench Development

When we were writing about TDD back in November 2011 during our TDD month, admittedly I had very little experience with it. The goal with TDD month was to spread the word and drum up a little interest in a … Continue reading

Posted in Functional Verification, TDD | Tagged , | Leave a comment

(Wasted) Effort Spent In Verification

I just spent a few minutes reading Harry Foster’s analysis of a functional verification study commissioned by Mentor Graphics and carried out by Wilson Research Group in 2010. There’s lots of good information in Harry’s analysis – there’s 9 posts … Continue reading

Posted in Functional Verification | Tagged , , | 9 Comments

Test Driven Development: Introducing the SVUnit Framework

Up until now, we’d been discussing the justification of using TDD in an ASIC development flow.   Hopefully, we’ve convinced you to try it.  In this post we’ll introduce a TDD framework that has been developed for SystemVerilog to help you use this … Continue reading

Posted in TDD, Tools, Uncategorized | Tagged , | 3 Comments