-
-
Recent Posts
-
Recent Comments
- nosnhojn on MiniTB: Finally… a Testbench Framework for Designers
- Michael Thompson on MiniTB: Finally… a Testbench Framework for Designers
- nosnhojn on UVM Report Mock Update
- Bryan on UVM Report Mock Update
- nosnhojn on MiniTB: Finally… a Testbench Framework for Designers
-
Catagories
Tags
Agile2011 agile@intel AgileSoC Cadence CDNLive collaboration constrained random DAC delivery DVCon EDA EDA360 Emacs embedded software emulation ESL Featured formal verification fun functionality functional verification guest blog incremental development iterative development Kanban linkedin Mentor Mentor Graphics org-mode pair programming Pomodoro project planning survey Requirements retrospectives SNUG svunit TDD TDD month teamwork usability User2User UVM UVM-UTest UVM Express Verification Horizons-
Tag Archives: TDD
Your Coverage Model is Wrong!
Here’s the scene: you’re a hardware engineer at a conference sitting in on a talk about functional coverage. You’re there because you think functional coverage is important. You think you do a good job of building functional coverage groups but … Continue reading
TDD Applied To Testbench Development
When we were writing about TDD back in November 2011 during our TDD month, admittedly I had very little experience with it. The goal with TDD month was to spread the word and drum up a little interest in a … Continue reading
(Wasted) Effort Spent In Verification
I just spent a few minutes reading Harry Foster’s analysis of a functional verification study commissioned by Mentor Graphics and carried out by Wilson Research Group in 2010. There’s lots of good information in Harry’s analysis – there’s 9 posts … Continue reading
Test Driven Development: Introducing the SVUnit Framework
Up until now, we’d been discussing the justification of using TDD in an ASIC development flow. Hopefully, we’ve convinced you to try it. In this post we’ll introduce a TDD framework that has been developed for SystemVerilog to help you use this … Continue reading