Tag Archives: svunit

SVUnit v3.1 Released

I just posted version 3.1 of SVUnit to sourceforge. If you’ve been waiting patiently for me to get rid of the makefiles, the wait is over. From here on, we’ve got a simple command line script to run SVUnit unit tests … Continue reading

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Posted in Functional Verification | Tagged | 4 Comments

SVUnit Scripting Proposal Version 2

I’ve had people asking about the SVUnit new scripting proposal I posted a few months back. I forgot about it for a while but now I’m back. I’ve taken some of the feedback I’ve received and folded it into a … Continue reading

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SVUnit Adds Support For Aldec Riviera-PRO

Here’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can … Continue reading

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SVUnit Scripting Proposal

I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, … Continue reading

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Upcoming Changes to SVUnit

After some back-and-forth with SVUnit users over the last several months, I reckon it’s finally time to get rid of the make user interface. Turns out, the incremental construction of the framework that make helped with isn’t all that necessary. … Continue reading

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AgileSoC.com Has It’s Own EDA Playground

Thanks to a new embeddable version of EDA Playground, you can now test-drive SVUnit right here on AgileSoC.com! Below, you’ll find the SVUnit example I explained back in December in a post called Demo SVUnit on EDAPlayground.com. Code editing is the same, … Continue reading

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SVUnit a Game Changer for this FPGA Team

Received a very nice endorsement for SVUnit today from a new user doing FGPA development and running Modelsim… Our company focuses on FPGAs.  SVUnit is a GAME CHANGER for FPGAs.  FPGAs are different from ASICs, in that bugs can be … Continue reading

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Unit Testing on Youtube, Cadence.com and DVCon

Started my day with some encouraging observations that I wanted to share… First, Victor Lyuboslavsky has posted a couple of youtube videos where he covers some of the basics of unit testing and SVUnit. These are good beginner videos that show … Continue reading

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Demo SVUnit on EDAPlayground.com

Time to introduce a great new development from an SVUnit early adopter: Victor Lyuboslavsky. Victor is a verification engineer at AMD in Austin that started with SVUnit back in February of 2012. He’s been using SVUnit on and off for … Continue reading

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Fast Sims Don’t Come From Fast Simulators

How many times have you sat through a conference talk or tutorial delivered by an AE from one of the big three EDA companies, the speaker announces a new version of their simulator, and the first follow-up question from the … Continue reading

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