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Tag Archives: svunit
UVM Report Mock Update
I’ve had some good feedback from a couple fellows using the report mock and today I released a new version to start incorporating it. SVUnit v1.4 includes a new UVM report mock. Two significant changes…
SVUnit v1.1 – Improved Module/RTL Support
Today, I posted a new v1.1 release of SVUnit on sourceforge. The “new” feature in version 1.1 is a refactored/simplified framework meant to increase usability, especially for people that want to do TDD or unit testing of RTL.
Your Coverage Model is Wrong!
Here’s the scene: you’re a hardware engineer at a conference sitting in on a talk about functional coverage. You’re there because you think functional coverage is important. You think you do a good job of building functional coverage groups but … Continue reading
Verifying UVM Error Conditions with SVUnit UVM Report Mock
Verifying error conditions and UVM testbench checkers just got easier! The SVUnit UVM report mock lets you automate testing of UVM errors and fatals to increase confidence that the checkers in your testbench are defect free. The SVUnit UVM report mock … Continue reading
SVUnit by Example: A Simple UVM Model
It was recently brought to my attention that I haven’t done a very good job of telling people about the examples that come with SVUnit. That’s unfortunate. The examples are there to help so if people don’t know they’re there … Continue reading
SVUnit 101 For Designers
If you read my last post, Why Use SVUnit?, you’ll see that someone responding to my announcement about SVUnit v0.1 on verificationguild.com pointed out that I haven’t done an outstanding job of explaining why people would actually use SVUnit. Seems the … Continue reading
Why Use SVUnit?
I recently came across the following comment on verificationguild.com in response to my posting of a link to the first publicly available, v0.1 version of SVUnit… I have attempted to read each of the blog posts about svunit, but they are … Continue reading
SVUnit And The Moment Of Truth
SVUnit isn’t just for early adopters anymore! Anyone can download and start using SVUnit to do TDD of complex ASIC and FPGA designs. For more info on getting and using SVUnit, go to the SVUnit home page. Bye-bye SVUnit development… … Continue reading
(Wasted) Effort Spent In Verification
I just spent a few minutes reading Harry Foster’s analysis of a functional verification study commissioned by Mentor Graphics and carried out by Wilson Research Group in 2010. There’s lots of good information in Harry’s analysis – there’s 9 posts … Continue reading
UVM Express Step 2: SVUnit with Covergroups and UVM Agents
I can honestly say that as of a couple weeks ago, I’ve gone further with SVUnit than I thought was realistic when I first starting looking at it. Having done more TDD, written more tests and recently finished step 2 … Continue reading