TagsAgile2011 agile@intel AgileSoC Cadence CDNLive collaboration constrained random DAC delivery DVCon EDA EDA360 Emacs embedded software emulation ESL fun functionality functional verification GoogleMock GoogleTest guest blog incremental development iterative development Kanban linkedin Mentor Graphics MiniTB org-mode pair programming Pomodoro project planning survey Requirements retrospectives SNUG svunit TDD TDD month teamwork usability User2User UVM UVM-UTest UVM Express Verification Horizons
Category Archives: Uncategorized
Heads-up that I just posted my end-of-conference summary of the Agile2014 conference in Orlando. In short, it was a great conference with some very promising signs for agile hardware. You can read my full report here. -neil
I’ve often heard the statement that hardware developers follow a more disciplined development process than software developers. What I haven’t heard much about is what it means to be disciplined and/or why that’s the case. So let’s open that discussion in hopes it … Continue reading
In the DVCon abstract I submitted last month, I mentioned a new verification component called the uvm_boat_anchor. The uvm_boat_anchor is top-secret development so not much was known at the time about this new component, even by me. For the abstract, … Continue reading
I don’t normally need much motivation to try something new on AgileSoC.com. So at the first sign people were interested in the idea of adding a forum to help facilitate discussion between hardware and software developers, I went ahead with … Continue reading
This may be a good idea… it also may be a terrible idea. Either way it’s worth a shot. You’ve heard of take your kid to work? Well, this is kind of like that except the kid is a hardware developer.
DVCon call for papers hit my inbox last week. This time around, to possibly save myself the effort, I figured it might be more productive to let other people decide whether or not mine is a topic they’d like to see … Continue reading
Through the hardware industry’s continuing infatuation with leading verification technologies – constrained-random verification, functional coverage, numerous fancy methodologies, intelligent testbenches and a host of others – the needs of designers have been thoroughly ignored. That changes with MiniTB.
Let’s have some fun, shall we? I’m looking for people to show their commitment to hardware quality by taking the My First SVUnit Test Challenge. It’s easy and perfect for anyone new to SVUnit.
Great final day at the Intel Agile and Lean Development Conference. It started with a keynote talk by Jim Tremlett of Rally, I had morning talk and an afternoon talk and filled in the rest of the time with hallway … Continue reading
So pretend you’ve dedicated about 5 years to something you believe in… I mean really believe in. At the beginning it seems like you’re the only person in on it (or 1 of 2 in my case considering Bryan was … Continue reading