Category Archives: Functional Verification

SVUnit v3.1 Released

I just posted version 3.1 of SVUnit to sourceforge. If you’ve been waiting patiently for me to get rid of the makefiles, the wait is over. From here on, we’ve got a simple command line script to run SVUnit unit tests … Continue reading

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Posted in Functional Verification | Tagged | 4 Comments

SVUnit Scripting Proposal Version 2

I’ve had people asking about the SVUnit new scripting proposal I posted a few months back. I forgot about it for a while but now I’m back. I’ve taken some of the feedback I’ve received and folded it into a … Continue reading

Posted in Functional Verification | Tagged | 1 Comment

Honey… I’m Being Eaten By A Bear: 10 Need to Know Tips

Last week I stumbled across a verification post that used my favorite verification graphic from the Wilson Research Group Functional Verification Survey that Mentor sponsors every few years. Here it is again for anyone that hasn’t seen it posted here … Continue reading

Posted in Functional Verification, TDD | 1 Comment

SVUnit Adds Support For Aldec Riviera-PRO

Here’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can … Continue reading

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SNUG Unit Testing Finale

SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I … Continue reading

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UVM-UTest File-a-Bug Challenge at SNUG

Time for another UVM challenge… So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll … Continue reading

Posted in Functional Verification | Tagged | 2 Comments

Help Wanted: Need Hecklers for my SNUG Unit Testing Talk

Next week is SNUG in San Jose and I’m looking forward to it. I’ll be presenting How UVM Makes the Case For Unit Testing in the Verification I track from 10:30-12 on Tuesday morning and would love to see some AgileSoC … Continue reading

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Forget About the Verification Gap

I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there … Continue reading

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You’re Either With Me Or You’re With: The UVM Register Package

Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was … Continue reading

Posted in Functional Verification | Tagged | 9 Comments

SVUnit Scripting Proposal

I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, … Continue reading

Posted in Functional Verification | Tagged | 4 Comments