Category Archives: Functional Verification

SVUnit Also Has a Logo

I figured the new user guide made SVUnit look like a real product. And since real products have a logo, I stayed up late one night and did logo. But if it has a logo, shouldn’t it also have a tagline? I guess, so now … Continue reading

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Posted in Functional Verification | Tagged | 1 Comment

SVUnit Now Has a User Guide

While I find reading EDA user guides hard enough, writing them is way worse, which is why I’ve avoided it for as long as I have. Alas, with usage of SVUnit growing pretty steady and people hinting for better instruction, I … Continue reading

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Tudor Timisescu, Welcome to SVUnit

Slacking off? Me?? I guess maybe I have been because someone finally got sick of waiting for me to get to a new SVUnit feature and added it themselves… …and that made me happy. As of 2 about weeks ago, Tudor … Continue reading

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SVUnit v3.1 Released

I just posted version 3.1 of SVUnit to sourceforge. If you’ve been waiting patiently for me to get rid of the makefiles, the wait is over. From here on, we’ve got a simple command line script to run SVUnit unit tests … Continue reading

Posted in Functional Verification | Tagged | 4 Comments

SVUnit Scripting Proposal Version 2

I’ve had people asking about the SVUnit new scripting proposal I posted a few months back. I forgot about it for a while but now I’m back. I’ve taken some of the feedback I’ve received and folded it into a … Continue reading

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Honey… I’m Being Eaten By A Bear: 10 Need to Know Tips

Last week I stumbled across a verification post that used my favorite verification graphic from the Wilson Research Group Functional Verification Survey that Mentor sponsors every few years. Here it is again for anyone that hasn’t seen it posted here … Continue reading

Posted in Functional Verification, TDD | 1 Comment

SVUnit Adds Support For Aldec Riviera-PRO

Here’s something to get Aldec users excited: SVUnit now supports Riviera-PRO. That means it’s no longer just Mentor Graphics, Cadence and Synopsys users that have the option of unit testing high quality Systemverilog RTL and testbench code, Aldec users can … Continue reading

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SNUG Unit Testing Finale

SNUG Silicon Valley is all wrapped up for another year. I think my talk on tuesday morning went pretty well. Finding the right angle for introducing agile hardware practices has been a real trick for me and this week I … Continue reading

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UVM-UTest File-a-Bug Challenge at SNUG

Time for another UVM challenge… So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll … Continue reading

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Help Wanted: Need Hecklers for my SNUG Unit Testing Talk

Next week is SNUG in San Jose and I’m looking forward to it. I’ll be presenting How UVM Makes the Case For Unit Testing in the Verification I track from 10:30-12 on Tuesday morning and would love to see some AgileSoC … Continue reading

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