UVM-UTest File-a-Bug Challenge at SNUG

Time for another UVM challenge…

So I’ve got SNUG coming up next week. I already posted a help wanted sign for hecklers that may want to hurl insults at me from 10:30 to 12 on Tuesday morning. That’s when I’ll be up on stage talking about UVM-UTest and how UVM makes the case for unit testing. Aside from the talk and the paper, I’ve also been pondering other ways to get the point across that unit testing is an effective way to verify hardware. I’ve been having trouble thinking of something appropriate… until tonight… I think… I hope… Continue reading

Forget About the Verification Gap

I always find the aftermath of DVCon interesting. I’ve never been to the conference but it always seems to be well covered. Between people live tweeting different sessions and others blogging, it always feels like I can be near there without being there.

The panel session that caught my eye this year was about something called the verification gap. In an article posted last week called Pointing Fingers in Verification, Brian Bailey made it sound like EDA representatives and users were doing their best to defer responsibility and deflect criticism when it comes to creating and closing the verification gap (it’s a good article… you should go read it when you’re done here).

I like these discussions so I’d like to add my 2 cents :). Continue reading

You’re Either With Me Or You’re With: The UVM Register Package

Let me take you back a few years to my first job as an ASIC verification engineer. It was 2000 and things were a lot different. The notion of “architecting a testbench” didn’t really exist the way it does today. Design was cool and verification was where junior engineers started. Constrained random verification hadn’t hit the mainstream. There wasn’t much functional coverage to speak of. I think Specman and Vera were around but the user-base was relatively small. There was no Systemverilog and there was no UVM. Basically, we were back in the stone age of directed testing. Any knucklehead could do it. Thankfully, I was perfectly qualified. Continue reading

SVUnit Scripting Proposal

I’ve gone through an overhaul of the SVUnit scripting. Specifically, the makefiles are out and a simpler build/run script is in. Most of what’s under the hood is the same (i.e. the construction of the systemverilog code framework). In short, create_svunit.pl + makefiles are out; runSVUnit is in.

Here’s a dump of the runSVUnit usage. Still subject to change so if you see something you don’t like or you don’t see something you would like, now is the time to bring it up :).

Screen Shot 2014-03-06 at 8.36.47 AM

Some additional notes… Continue reading

Upcoming Changes to SVUnit

After some back-and-forth with SVUnit users over the last several months, I reckon it’s finally time to get rid of the make user interface. Turns out, the incremental construction of the framework that make helped with isn’t all that necessary. It also seems some hardware developers get a little nervous around makefiles (admittedly, they make me nervous at times). In response, I’ll be putting together a simpler build/run script in place of what’s there now.

If you’re in favour of a new scripting interface and would like to help out by critiquing a first release, please let me know at neil.johnson@agilesoc.com.

I have unit tests for the scripting to rely on for quality so what I end up with should be pretty solid. Still, it’d be nice for me to get a few opinions before I release it.

-neil

AgileSoC.com Has It’s Own EDA Playground

Thanks to a new embeddable version of EDA Playground, you can now test-drive SVUnit right here on AgileSoC.com!

Below, you’ll find the SVUnit example I explained back in December in a post called Demo SVUnit on EDAPlayground.com. Code editing is the same, running a sim is the same. The only difference (because of our wordpress stylesheet) is that the frame is a little narrower. Other than that, this is our own EDAPlayground right here on AgileSoC.com.

This example is an easy introduction to SVUnit. Start with the instructions in the left pane (you can adjust the pane size to make it easier to read and edit). Then you can bounce over to the design pane. To simulate the example, look for the Screen Shot 2014-02-15 at 11.52.47 AM button in the top right. Click that and you’ll see the run button.

[iframe src=”http://embed.edaplayground.com/embed/x/7Q?from=http://www.agilesoc.com&button=run&panes=2″ name=”EDAPlayground” width=”100%” height=”700″ frameborder=”0″]

Good luck! Please use the comments to let us know what you think!

-neil

SVUnit a Game Changer for this FPGA Team

Received a very nice endorsement for SVUnit today from a new user doing FGPA development and running Modelsim…

Our company focuses on FPGAs.  SVUnit is a GAME CHANGER for FPGAs.  FPGAs are different from ASICs, in that bugs can be fixed while the product is in the field.  SVUnit is a lot less cumbersome than traditional verification.  This allows R&D to push a design into test sooner with similar confidence.

SVUnit advantages:

  • quick to setup
  • does not require expensive licenses
  • easy to test individual modules and therefore pin point bugs earlier in development, making the bugs less expensive

(Here’s something cool.  I am using the altera starter edition of modelsim under linux.  There is a lot of validation people can do without needing a license.)

Nice to hear comments like this. SVUnit is supposed to be clean and user friendly so it’s nice to add another happy user. If you’re ready for a game changing experience, the SVUnit Getting Started page is a good place to start.

-neil

PS: Out-of-the-box, SVUnit now supports Modelsim in addition to VCS, Incisive and Questa.

Beware of Progress

skullIf you’re a hardware developer, here’s a verilog coding exercise you should never, ever attempt.

Ever.

No one in their right mind would try it; not even dare someone else to try it. The stakes are way too high and you can’t risk your precious time futzing away on some impossible coding exercise. That’s right: impossible. This coding exercise is like doing a 49×49 sudoku on a double black diamond on a 50ft wave at high noon in the middle of a desert that has lots of spiders and rabid skunks… blindfolded. Continue reading

New Year’s Product Development at Cadence, Mentor and Synopsys

With Cadence recently releasing an eUnit test framework with Specman, I figured now would be a good time to suggest a 2014 new year’s resolution for each of the Big 3:

Make functional verification manageable by releasing a SystemVerilog unit test framework with your simulator.

Don’t worry if that sounds complicated because it isn’t. In a couple months, tops, you could have everything you need to package a first release. All it takes is 4 easy steps.

NOTE (to Mentor/Synopsys): Cadence is winning this race so far. If I had to guess, I’d say that their recent additions to Specman mean they’re considering something similar for SystemVerilog if not well into its development. Continue reading