Poll: Unit Testing Abstract for DVCon 2014… Yay or Nay?

DVCon call for papers hit my inbox last week. This time around, to possibly save myself the effort, I figured it might be more productive to let other people decide whether or not mine is a topic they’d like to see at DVCon. I’ve got a draft title and abstract so far…

How UVM-1.1d Makes the Case For Unit Testing

In six weeks, two verification engineers discovered 10 defects in the UVM-1.1d release. The defects were not lurking in the shadows of complex corner scenarios; it didn’t take hours of constrained-random stimulus to discover them; nor was there any need for functional coverage with intelligent feedback. These were simple, obvious defects discovered with an equally simple and obvious technique. It’s called unit testing and it comes from software development where the value placed on code quality and maintainability is higher than what we aspire to in hardware.

UVM-UTest is an open-source project with the goal of demonstrating how unit testing can be used to bring software level quality and maintainability to design and testbench code. This paper documents the development of UVM-UTest, how it was conceived, statistics and style for unit tests written, its success in terms of defects found in UVM-1.1d, the lessons learned and recommendations for applying unit testing beyond the UVM. The paper concludes by introducing a new UVM component, the uvm_boat_anchor, that further demonstrates the perils of continuing to ignore the value of this basic yet entirely necessary technique.

I’ve submitted proposals twice in the last few years. Neither was accepted. Agile development and test-driven development – the topics I’ve submitted – aren’t your average mainstream, audience grabbing topics so that wasn’t overly surprising. Maybe this proposal is different. Or maybe it’s not. Either way, I’m leaving it for you to decide.

Would you like to see how UVM-1.1d makes the case for unit testing at DVCon in March, 2014?

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If there’s enough interest, I’ll submit it and see what happens. If you really like the abstract, share it with your colleagues so they can vote, too. Or if you hate it, may as well share it, anyway. I don’t mind people seeing my incredibly terrible ideas. I’ll just entertain myself with it.

Proposals are due Aug 27th so share the link and get your votes in asap!

-neil

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About nosnhojn

I have been working in ASIC and FPGA development for more than 12 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. My specialty for most of that time has been RTL functional verification where I have had a chance to work with some very experienced people and learn state of the art techniques. I really enjoy the challenges of being a verification engineer but as of late have come to wonder what lies beyond my verification bubble. That's lead me to agile software development and project management. There is a massive amount of material out there related to agile development. All of it is interesting and most of it should be applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully! You can find me at neil.johnson@agilesoc.com.
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3 Responses to Poll: Unit Testing Abstract for DVCon 2014… Yay or Nay?

  1. Bryan says:

    UVM is always a big topic at DVCon, so I think that tying your topic in with UVM gives you a good chance of getting in. You might remove this part, “…where the value placed on code quality and maintainability is higher than what we aspire to in hardware.” A little inflammatory :-) Oh, and the boat anchor jab too, it might not endear you to the panel.

    • nosnhojn says:

      Thanks Bryan! Nice that you’ve picked out 2 of the key parts to the paper. Gotta keep those. it’d be way too boring without them ;)

      -neil

  2. tobias says:

    Neil, would love to see your submission being accepted. I think you’ll need a more attracting title and less “hardware versus software”. Otherwise you’ll move traditional hw developers into denial mode ;-) Can you make a case how long it would take to debug a testbench that is affected by the buggy code one of the unit tests found? Then use this as your headline, e.g. UVM1.1e – saves 1 year of precious debug time around the globe.

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