Are You Ready for the UVM-UTest Challenge?

We did our first UVM-UTest challenge on Friday. It went surprisingly well so now we’re going out on a limb by inviting others to take the challenge.

The “rules” of the challenge are:

  • A team of 3 has one hour to break our unit tests (we used a lunch hour so it was like a lunch-n-learn… except it wasn’t boring).
  • If a team can make functional changes to the uvm-1.1d library that our tests do not detect, you win. If our unit tests detect the functional changes you make, the unit tests win. Pretty simple.
  • We guide you through the challenge so you know what code/classes you’re able to change (we also keep notes for where we can improve our test suite).

As an example, the results from the challenge we did on Friday were 2 teams of 3 found 6 holes in our unit test suite. Technically, we lost… though there were lots of changes the unit tests did detect so it wasn’t a total loss!

A couple of encouraging comments we received on Friday during the challenge:

  • you guys are catching a lot of stuff I thought might slip through
  • useful exercise that got me thinking about how easy it would be to break my code

We thought it was a useful demonstration of the value of unit tests and how unit tests can increase code quality, which is why we’d like to open it up to others.

If you’ve got a team that’s interested, you can let us know by sending me an email at: neil.johnson@agilesoc.com.

NOTE: anyone can do this. If you know how to delete or change systemverilog code, your chance of winning is pretty good. No knowledge of UVM is required.

If you want to know more about UVM-UTest before you decide, you can find that on the UVM-UTest project page.

-neil

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About nosnhojn

I have been working in ASIC and FPGA development for more than 12 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. My specialty for most of that time has been RTL functional verification where I have had a chance to work with some very experienced people and learn state of the art techniques. I really enjoy the challenges of being a verification engineer but as of late have come to wonder what lies beyond my verification bubble. That's lead me to agile software development and project management. There is a massive amount of material out there related to agile development. All of it is interesting and most of it should be applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully! You can find me at neil.johnson@agilesoc.com.
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