How Do You Feel About The UVM?

I’ve had a lot of reading and commenting on my last post Time to Blow Up UVM. Now I’m looking for an anonymous show of hands to see if I’m on the mark or completely out to lunch regarding UVM.

How do you feel about the Universal Verification Methodology?

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-neil

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About nosnhojn

I've been working in ASIC and FPGA development for more than 13 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. In 2008 I took an interest in agile software development. I've found a massive amount of material out there related to agile development, all of it is interesting and most of it is applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully. I've been fortunate to have the chance to speak about agile hardware development at various conferences like Agile2011, Agile2012, Intel Lean/Agile Conference 2013 and SNUG. I also do lunch-n-learn talks for small groups and enjoy talking to anyone with an agile hardware story to tell! You can find me at neil.johnson@agilesoc.com.
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3 Responses to How Do You Feel About The UVM?

  1. Michael Thompson says:

    Hi Neil. While I’m sympathetic to your position, it’s important to keep all this in perspective. It’s doesn’t matter if its eRM, RVM, AVM, OVM, VMM or UVM, the cost/benefit of using one of these methodologies is always going to tilt in favour of using a formal methodology. It’s true that there is a significant cost/effort barrier to overcome if your team is going to realize any benefits from a methodology. In my experience, this cost is always less than the benefits. Spend time with it, learn to make it work for you. All of these methodologies are incredibly flexible, so your team can cherry pick the features that meet their needs.

    Lets not go throwing the baby out with the bath water. :-)

    Cheers,
    —mike

  2. Gareth says:

    hey Mike,

    You’re certainly not going to sympathize with my position, then – what I wouldn’t do to get rid of SystemVerilog, too.

    Baby? Bath water? I don’t even want the damned tub! :)

  3. Honza Vosalik says:

    The UVM has a nice approach to register models by its register model (once you learn how to use it). This can significantly make the work easier during the time when the implementation of both the design and verification is running and the registers are often changing. I know this could also be done in a non-UVM enviroment by using structures and implementing your own accesss functions, but I think the UVM reg model approach is pretty good.

    On the other hand, since UVM has soo many classes and objects etc., it takes much longer to compile testcases and this just slows down your work if you are developing testcases.

    UVM is also very complex and without learning quite a lot first, it can be hard to use.

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