(Wasted) Effort Spent In Verification Rerun

I ran across this graphic in some old material I was going through today. Thought it was worth a reminder. 2 hrs 33min and 36sec everyday is a lot of time, no?

-neil

 

 

About nosnhojn

I have been working in ASIC and FPGA development for more than 12 years at various IP and product development companies and now as a consultant with XtremeEDA Corp. My specialty for most of that time has been RTL functional verification where I have had a chance to work with some very experienced people and learn state of the art techniques. I really enjoy the challenges of being a verification engineer but as of late have come to wonder what lies beyond my verification bubble. That's lead me to agile software development and project management. There is a massive amount of material out there related to agile development. All of it is interesting and most of it should be applicable to hardware development in one form or another. So I'm here to find what agile concepts will work for hardware development and to help other developers use them successfully! You can find me at neil.johnson@agilesoc.com.
This entry was posted in TDD. Bookmark the permalink.

One Response to (Wasted) Effort Spent In Verification Rerun

  1. nosnhojn says:

    Q. What can we do to cut down the amount of time spent debugging code?

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>